ASYNCHRONOUS BIT-SERIAL DATA RECEIVER

申请公布号：

CA1043428(A)

申请号：

CA19750239151

申请日期：

1975.11.07

申请公布日期：

1978.11.28

申请人：

INTERNATIONAL STANDARD ELECTRIC CORPORATION

发明人：

FELLINGER, FRANK

分类号：

F02B75/02;H04L5/24;H04L7/033;H04L7/04;H04Q11/06;(IPC1-7):04L7/00

主分类号：

F02B75/02

摘要：

<p>The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register, An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register. In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flipflop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling centered over each data bit.</p>