DIFFERENTIAL LOGICAL CIRCUIT FOR MULTIVALUED ORTHOGONAL AMPLITUDE MODULATION
- 申请公布号：
- JPS59112749(A)
- 申请号：
- JP19820222629
- 申请日期：
- 1982.12.18
- 申请公布日期：
- 1984.06.29
- 申请人：
- FUJITSU KK
- 发明人：
- KATOU TADAYOSHI
- 分类号：
- H04L27/34
- 主分类号：
- H04L27/34
- 摘要：
- PURPOSE:To perform code conversion even in multivalued orthogonal amplitude modulation by providing a logical circuit which superposes signals of the 1st, the 2nd, and the 3rd paths that divide the signal plane of orthogonal amplitude modulation into four quadrants. CONSTITUTION:Binary signals P1 and q1 of the 1st bus which divides the signal plane of orthogonal amplitude modulation into four quadrants are inputted to a four-phase PSK transmitting logical circuit 13, whose output signals P1' and q1' are ORed exclusively by an element E1, whose output is supplied to an inverting logical circuit 15. The circuit 15 inverts binary signals P2 and q2 of the 2nd path which further divides the four- divided quadrants into four in polarity when the output of AND A1 between the E1 output and the output of exclusive OR E2 between the binary signals P2 and q2 is 1. Binary signals P3 and q3 of the 3rd path which further divides quadrants divided by the 2nd path into four are inptted to an inverting logical circuit 17 and ORed E3 exclusively, and when the output of AND A2 between the E3 output and E2 output is 1, the signals P3 and q3 are inverted in polarity. A Gray encoding orthogonal amplitude modulator 11 imposes 64-phase modulation upon outputs of the circuits 13, 15, and 17 to generate an output. The signal is demodulated on a reception side in the reverse route to output signals P1-P3 and q1-q3.
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