DECIMAL FRACTION MULTIPLIER

申请公布号：

JPH01100626(A)

申请号：

JP19870258880

申请日期：

1987.10.14

申请公布日期：

1989.04.18

申请人：

MATSUSHITA ELECTRIC IND CO LTD

发明人：

MIZUGUCHI HIROSHI

分类号：

G06F7/53;G06F7/508;G06F7/52;G06F7/523;G06F17/10

主分类号：

G06F7/53

摘要：

PURPOSE:To directly multiply an integer by a decimal fraction by being equipped with a bit discriminating means, a switching means to be operated with an output, a feedback means of an adder, and a multiplication control circuit. CONSTITUTION:A switch group to be operated by the output of a bit AND circuit 51 of a bit discriminating block 10 is provided at a multiplicand transferring path to an adder 50, and the output of the adder is fed back through a feedback bus 60 and a right shifter 53 on an input side. A bit position selective signal is supplied from a multiplication control circuit 55 through a multiplier and a decoder 54 to the AND circuit 51, and an adding instruction ADD is also given to the adder 50. The AND circuit 51 opens a switch group 52 at the time of '0', and a zero is supplied on the multiplicand side of the adder 50. Since the value of the multiplier is successively discriminated from the highest-order bit in units of a bit, the bit position selective signal is given for the prescribed times set beforehand, and the multiplier in the adder is controlled, the integer can be directly multiplied by the decimal fraction.