ECL gate array with collector resistance compensation for distance from power supply pad

申请公布号:
US4866303(A)
申请号:
US19840676836
申请日期:
1984.11.30
申请公布日期:
1989.09.12
申请人:
FUJITSU LIMITED
发明人:
KANAI, YASUNORI;NAWATA, KAZUMASA;SHIMIZU, MITSUHISA
分类号:
H03K19/003;H03K19/086;H03K19/173
主分类号:
H03K19/003
摘要:
An ECL gate array comprising a plurality of basic cells. Each basic cell has a pair of emitter-coupled transistors, and a load connected between the collectors of the transistors and a power supply line. In accordance with a circuit design information, the resistance value of the load can be selected for increasing a noise margin of the output logic levels without deteriorating the switching speed.
专利推荐
移动版 | 电脑版 | 返回顶部