MULTI-PROCESSOR DEVICE

申请公布号：

JPH03229350(A)

申请号：

JP19900025774

申请日期：

1990.02.05

申请公布日期：

1991.10.11

申请人：

MATSUSHITA ELECTRIC IND CO LTD

发明人：

OGISU MIKIO

分类号：

G06F15/16;G06F9/52;G06F15/177

主分类号：

G06F15/16

摘要：

PURPOSE:To execute the synchronization processing at a high sped in the case of executing the synchronization processing between plural CPUs by constituting the device so that a prescribed signal is inputted to an input terminal of a master CPU and other all non-master CPUs recognize a fact that the mask processing is ended. CONSTITUTION:When a master CPU ends the processing of its own task, a prescribed signal is outputted from an output terminal 2, and one of other non-master CPUs inputs it. Subsequently, when other non-master CPUs end the processing of its own task, its own input terminal is connected to the output terminal, therefore, when the task processing of all non-master CPUs is ended, the prescribed signal returns to the input terminal 1 of the master CPU, and it is recognized that the task processing of all the CPUs is ended. In such a way, in the case of executing the synchronization processing between plural CPUs, the synchronization processing reception is not executed by a software processing but executed synchronously or non-synchronously to a system clock by a hardware. Accordingly, the processing can be executed at a high speed.