VERIFYING METHOD FOR FILM PLOTTING DATA FOR FORMING PRINTED WIRING BOARD PATTERN
- 申请公布号：
- JPH043268(A)
- 申请号：
- JP19900104604
- 申请日期：
- 1990.04.20
- 申请公布日期：
- 1992.01.08
- 申请人：
- ADVANTEST CORP
- 发明人：
- KOBAYASHI HIROSHI
- 分类号：
- G03F1/00;G06F17/50;H05K3/00
- 主分类号：
- G03F1/00
- 摘要：
- PURPOSE:To exactly verify the film plotting data in a short time by checking whether a physical connecting relation between each part pattern of a printed wiring board is different from a connecting relation on a design or not, and checking whether a clearance between each part pattern is smaller than the minimum allowable value or not. CONSTITUTION:From film plotting data for forming a printed wiring board pattern, physical connecting information for showing a physical connecting relation between each part pattern of a printed wiring board is generated, its physical connecting information is collated with logical connecting information for showing a connecting relation on a design between each part pattern and whether the physical connecting relation between each part pattern is different from the connecting relation on the design or not is checked, and also, from the film plotting data, whether a clearance between each part pattern is smaller than the minimum allowable value or not is checked. These checks can all be executed electronically and automatically by using a computer. In such a way, the film plotting data can be verified exactly in a short time.
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