Equal length symmetric computer bus topology

申请公布号：

US5548734(A)

申请号：

US19950368716

申请日期：

1995.01.04

申请公布日期：

1996.08.20

申请人：

INTEL CORPORATION

发明人：

KOLINSKI, JERZY;SPRIETSMA, JOHN;PAWLOWSKI, STEPHEN;SCHAECHTERLE, HENRY

分类号：

G06F13/40;H05K1/02;H05K1/14;(IPC1-7):G06F13/00

主分类号：

G06F13/40

摘要：

An equal length symmetric computer bus topology. The equal length symmetric computer bus topology provides a bus signal path to a number of bus nodes. Each bus signal path extends from each node on the computer bus to a central junction point. The bus signal paths are of equal length and have identical electrical characteristics. The equal length symmetric computer bus topology minimizes the effect of transmission line reflections upon the bus signals. The equal length symmetric computer bus topology also causes very little clock skew.