SEMICONDUCTOR MEMORY

申请公布号：

JP2001135076(A)

申请号：

JP19990317383

申请日期：

1999.11.08

申请公布日期：

2001.05.18

申请人：

NEC CORP

发明人：

ONODERA TADASHI

分类号：

G11C11/401;G11C11/407

主分类号：

G11C11/401

摘要：

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which an adjacent banks sharing a sense amplifier are not activated simultaneously even when a bank to be activated is erroneously specified or a power source is applied. SOLUTION: Banks B0-B2 are operated independently, for example, a bank B1 shares a train of sense amplifiers 3-01, 3-12 with adjacent banks B0, B2. When a bank enable-signal generating circuit 10-1 generates a bank enable-signal BE1 for activating the bank B1, the circuit 10-1 validates a bank enable-signal BE1 only when neither of adjacent banks B0, B2 are activated. A row decoder 1-1 and a control circuit 11-1 validate the sense amplifier enable-signal SE1 for activating word lines WL1, and the train of sense amplifiers 3-01, 3-12, a pre-charge signal PDL1 for activating pre-charge circuits 2-1a, 1-1b, and a switch control signal TG1 for controlling a conduction state of switches 5-1a, 5-1b only when the bank enable-signal BE1 is valid.