SICHERHEITSKOPROZESSOR ZUR VERBESSERUNG DER COMPUTERSYSTEMSICHERHEIT
- 申请公布号：
- DE69832082(D1)
- 申请号：
- DE1998632082
- 申请日期：
- 1998.02.10
- 申请公布日期：
- 2005.12.01
- 申请人：
- HELBIG SR., WALTER A.
- 发明人：
- HELBIG, A.;ACKERMAN, H.
- 分类号：
- G06F12/14;G06F1/00;G06F9/38;G06F21/00;G06F21/22;G06F21/24;(IPC1-7):H04K1/00;G06F11/34;G06F11/00
- 主分类号：
- G06F12/14
- 摘要：
- A security enhanced computer system arrangement includes a coprocessor (10) and a multiprocessor logic controller (38) inserted into the architecture of a conventional computer system. The coprocessor and multiprocessor logic controller is interposed between the CPU of the conventional computer system to intercept and replace control signals that are passed over certain of the critical control signal lines associated with the CPU. The CPU is released by allowing control signals to again pass between it and the computer system. Isolating the CPU control signal from the remainder of the computer system, allows a multiprocessor logic controller (38) to interrupt the normal computer system operation at any time and permit the coprocessor to check digital signatures of any firmware or software in the computer system. The multiprocessor logic controller arrangement thereby isolates the CPU of the conventional computer system from the remainder of the conventional computer system, permitting separate control over the CPU and separate control over the remainder of the computer system.
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