METHOD FOR FABRICATING PARTIAL SOI WAFER

申请公布号：

KR20100053910(A)

申请号：

KR20080112789

申请日期：

2008.11.13

申请公布日期：

2010.05.24

申请人：

HYNIX SEMICONDUCTOR INC.

发明人：

KIM, MYUNG OK

分类号：

H01L21/20

主分类号：

H01L21/20

摘要：

PURPOSE: A method for manufacturing a partial silicon-on-insulator wafer is provided to prevent the contamination of a chamber due to metal element by forming a layer including non-metal element as an insulation pattern or a metal pattern on the wafer. CONSTITUTION: An insulation pattern is formed on a first silicon layer(401A). Contaminants and a damage layer on the first silicon layer are removed. A second silicon layer is formed on the first silicon layer by an epitaxial growth method. The second silicon layer is planarized. The second silicon layer is etched to form a trench. An element isolation layer(417B) is formed to fill the trench.