Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violation

申请公布号：: US8291365(B2)
申请号：: US20060327226
申请日期：: 2006.01.06
申请公布日期：: 2012.10.16
申请人：: HE LIMIN;YAO SO-ZEN;DENG WENYONG;CHEN JING;CHAO LIANG-JIH;CADENCE DESIGN SYSTEMS, INC.
发明人：: HE LIMIN;YAO SO-ZEN;DENG WENYONG;CHEN JING;CHAO LIANG-JIH
分类号：: G06F17/50;H01L21/82
主分类号：: G06F17/50
摘要：: An innovative routing method for an integrated circuit design layout. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.