SEMICONDUCTOR MEMORY APPARATUS

申请公布号：

JP2005285283(A)

申请号：

JP20040101356

申请日期：

2004.03.30

申请公布日期：

2005.10.13

申请人：

NEC ELECTRONICS CORP

发明人：

SUGAWARA HIROSHI

分类号：

G11C16/06;G06F13/00;G11C7/06;G11C7/10;G11C7/14;G11C7/18;G11C11/4063;G11C11/409;G11C11/413;G11C11/419;G11C16/26;(IPC1-7):G11C16/06

主分类号：

G11C16/06

摘要：

<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which execution operation can be performed at high speed in a semiconductor memory apparatus controlling a data bus. <P>SOLUTION: In the semiconductor memory apparatus, a first sense amplifier part (15-1-j, 21-1) outputs an output signal to a first data bus (20') in accordance with a first selection signal (A). A second sense amplifier part (15-4-j, 22-1) outputs an output signal to a second data bus (20'') in accordance with a second selection signal (B). An inversion part (30) reverses a signal level of the output signal applied to one side of data bus of the first data bus (20') and the second data bus (20'') and outputs it to the other side of the first data bus (20') and the second data bus (20''). An equalize-circuit (33) equalizes a signal level applied to the first data bus (20') and a signal level applied to the second data bus (20''). A bus driver circuit (23) reverses a signal level applied to the second data bus (20'') or does not reverse, and outputs it to a third data bus (20'''). <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>