Shift register

申请公布号：

US9384853(B2)

申请号：

US201314140776

申请日期：

2013.12.26

申请公布日期：

2016.07.05

申请人：

LG Display Co., Ltd.

发明人：

Jang Yong-Ho

分类号：

G11C19/00;G11C19/28;G09G3/32

主分类号：

G11C19/00

代理机构：

Dentons US LLP

代理人：

Dentons US LLP

地址：

Seoul KR

摘要：

A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

主权项：

1. A shift register comprising a plurality of stages, each of the stages outputting k composite pulses (where k is a natural number greater than 1), each of the composite pulses comprising an A-scan pulse and a B-scan pulse, wherein at least one of the stages comprises: an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse; at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the at least one B-reset node and any one BB-clock pulse; and a scan output controller for generating k A-scan pulses based on at least one of the voltage at the A-set node and the A-carry pulse and k A-clock pulses, generating k B-scan pulses based on the B-carry pulse and k B-clock pulses, and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as a corresponding one of the composite pulses.