Method and apparatus for suppressing metal-gate cross-diffusion in semiconductor technology

申请公布号:
US9385127(B2)
申请号:
US201313973616
申请日期:
2013.08.22
申请公布日期:
2016.07.05
申请人:
XILINX, INC.
发明人:
Lin Qi;Pan Hong-Tsz;Wu Yun;Nguyen Bang-Thu
分类号:
H01L21/70;H01L27/092;H01L21/8238
主分类号:
H01L21/70
代理人:
Chan Gerald;Taboada Keith;Brush Robert M.
地址:
San Jose CA US
摘要:
An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.
主权项:
1. An inverter, comprising: a PMOS comprising: a p-type source region,a p-type drain region,a p-channel region between the p-type source region and the p-type drain region, anda PMOS metal gate region comprising one or more PMOS work function layers located above an insulating layer and a PMOS metal gate layer located above the one or more PMOS work function layers, the PMOS metal gate layer consisting of metal; a NMOS, comprising: an n-type source region,an n-type drain region,an n-channel region between the n-type source region and the n-type drain region, anda NMOS metal gate region comprising one or more NMOS work function layers located above the insulating layer and a NMOS metal gate layer located above the one or more NMOS work function layers, the NMOS metal gate layer consisting of metal; the insulating layer being above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact having a frusto-conical cross-section and being disposed between the NMOS metal gate region and the PMOS metal gate region.
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