SIGNAL DELAY DEVICE

申请公布号：

JPS62203415(A)

申请号：

JP19860046549

申请日期：

1986.03.04

申请公布日期：

1987.09.08

申请人：

MATSUSHITA ELECTRIC IND CO LTD

发明人：

HIRAI KIYOSHI;SEKIMOTO KUNIO

分类号：

H03K5/135;H04N5/95;H04N5/953

主分类号：

H03K5/135

摘要：

PURPOSE:To attain ease of circuit integration and to make the temperature effect hardly susceptible by providing the 2nd extracting means extracting a delay output in response to the output of the 1st extracting means from the 2nd delay device to retard an input signal digitally. CONSTITUTION:An output of each stage of the 1st counter frequency-dividing a clock signal is extracted by using a signal retarded by the 1st delay means whose delay is variable from the maximum frequency division output of the 1st counter and the delay output in response to the output of the extracting means is extracted from the 2nd delay means to retard the input signal digitally, the delay signal output corresponding to the delay of the 1st delay means and synchronously with the clock signal is obtained. Only when the reset signal is at the outside of the window pulse, the 2nd counter is reset and the output of each stage of the 1st counter is extracted by using a window pulse or its equivalent signal.