LATCH CIRCUIT AND REGISTER CIRCUIT

申请公布号：

JP2000357943(A)

申请号：

JP19990169769

申请日期：

1999.06.16

申请公布日期：

2000.12.26

申请人：

NEC CORP

发明人：

TAKAHASHI HIROYUKI

分类号：

H03K3/356;H03K3/012;H03K3/037;H03K3/3562;(IPC1-7):H03K3/037

主分类号：

H03K3/356

摘要：

PROBLEM TO BE SOLVED: To reinforce the supply drive force of clock signals to respective transfer circuits and holding circuits at the supplying of the clock signals to a latch circuit which contains the transfer circuits and the transfer circuits for holding data and a register circuit where the latch circuits are connected for plural stages. SOLUTION: In a latch circuit where signals are sequentially outputted while they are temporarily stored in accordance with input signals, a transfer circuit which inputs a reference clock(CLK), inverters INV1 to INV5 inverting the output of the transfer circuit, a second inverter inverting the outputs of the inverters and a transfer circuit for holding data, which inputs the output of the second inverter and outputs it to the input of the inverter, are installed. A second CLK, which rises after the rise of CLK with a prescribed delay time and falls with the fall of CLK is supplied to the gate of the transfer circuit for holding data.